Logic circuit, timing generator circuit, display device, portable terminal

ABSTRACT

When a buffer is formed by using transistors having large element characteristic variations, the deviation of the timing between the input clock pulse and the reset pulse is likely to occur. When the deviation of the timing becomes larger, a malfunction is caused to occur, and an operation margin becomes smaller with respect to the variations of the element characteristics. In a timing generation circuit, which is formed on an insulating substrate and which has two TFFs ( 12, 13 ), for generating a dot clock DCK and a horizontal clock HCK whose frequencies are different in synchronization with a master clock MCK which is input external to the substrate, separate reset pulses drst and hrst are generated at a pulse generation circuit  15  with respect to the two TFFs ( 12, 13 ), and a resetting operation is performed at separate timings. Thus, a large operation margin can be ensured even when each circuit is formed by using TFTs having large element characteristic variations and a rough process rule.

TECHNICAL FIELD

[0001] The present invention relates to a logic circuit, a timinggeneration circuit, a display device, and a portable terminal. Moreparticularly, the present invention relates to a logic circuit which isformed on an insulating substrate by using transistors having largecharacteristic variations, a timing generation circuit using the logiccircuit, a display device using the timing generation circuit as one ofperipheral driving circuits, and a portable terminal having incorporatedtherein the display device as a screen display section.

BACKGROUND ART

[0002] A conventional example of a timing generation circuit, which isone type of logic circuit, is shown in FIG. 7. The timing generationcircuit according to this conventional example is configured to have alevel-shift circuit 101, and two flip-flops which are cascade-connectedin sequence to the output thereof, that is, T-type flip-flops(hereinafter referred to as “TFFs”) 102 and 103 in this example. Thelevel-shift circuit 101 level-shifts (level-converts) a master clock MCKof a low voltage amplitude, which is input externally, into a masterclock lsmck of a high voltage amplitude. This master clock lsmck issupplied via a buffer 104 to a circuit which operates by using themaster clock lsmck as a reference.

[0003] The TFF 102 generates a dot clock DCK by frequency-dividing themaster clock lsmck. This dot clock DCK is supplied via a buffer 105 to acircuit which operates by using the dot clock DCK as a reference. TheTFF 103 generates a horizontal clock HCK by further frequency-dividingthe dot clock DCK. This horizontal clock HCK is supplied to a circuitwhich operates by using the horizontal clock HCK as a reference.

[0004] The TFFs 102 and 103 are reset in accordance with a reset pulsewhich is given externally, for example, at a 1H (H is a horizontalperiod) period. Here, wiring for transmitting the reset pulse to theTFFs 102 and 103 has a wiring capacity, a transistor input capacity, anda cross capacity with the other wiring. For this reason, a configurationis adopted in which the driving capability for a load capacity isincreased by using a buffer 106 having a capability enough to drive suchload capacities.

[0005] In the timing generation circuit having the above-mentionedconfiguration, in a case where each circuit part is formed by usingtransistors having large characteristic variations, the deviation oftimings between each input clock pulse of the TFFs 102 and 103 and thereset pulse is likely to occur. When the deviation of timings becomeslarger, problems arise in that a malfunction occurs, and the operationmargin becomes smaller with respect to element characteristicvariations.

[0006] Here, the circuit operation of the timing generation circuithaving the above-mentioned configuration will be described withreference to the timing charts in FIGS. 8A and 8B.

[0007] During the normal operation, as shown in FIG. 8A, the TFFs 102and 103 repeat the operation of their state being inverted insynchronization with the rise of the input clock pulse, therebygenerating an output pulse whose period is twice as long as that of theinput clock pulse. Furthermore, when a low-level reset pulse is given,the output pulse becomes a low level as a result of being reset at thetiming of the fall thereof, and the output pulse shifts to a high levelat the rise timing of the first input clock pulse after the reset pulseshifts to a high level. Thereafter, the TFFs 102 and 103 continue togenerate the output pulse in synchronization with the input clock pulseover the period in which the next reset pulse is given.

[0008] On the other hand, during malfunction such as the relative timingrelationship between the input clock pulse and the reset pulse beingdeviated due to element characteristic variations, for example, as shownin FIG. 8B, when the reset pulse which occurs in a period in which theinput clock pulse is at a low level during the normal operation tap(FIG. 8A) occurs in a period in which the input clock pulse is at a highlevel, the reset operation is continued also after the rise timing ofthe next input clock pulse. Consequently, a malfunction of the polarityof the output pulse after the reset occurs.

[0009] The deviation of the relative timing relationship between theinput clock pulse and the reset pulse occurs from the difference in theamount of delay between the circuits which generate these pulses, thatis, the level-shift circuit 101 and the TFFs 102 and 103, and the buffer107. In a case where these circuits are formed by using Thin-FilmTransistors (TFTs) having large element characteristic variations andhaving a rough process rule (for example, 3.5 μm), the amount of delayis large, and, in particular, the difference is likely to occur.

[0010] The present invention has been made in view of theabove-described problems. An object of the present invention is toprovide a logic circuit capable of ensuring a large operation margineven when it is formed by using transistors having variations incharacteristics and having a rough process rule, a timing generationcircuit using the logic circuit, a display device using the timinggeneration circuit as one of peripheral driving circuits, and a portableterminal having incorporated therein the display device as a displayoutput section.

DISCLOSURE OF INVENTION

[0011] The logic circuit of the present invention includes a pluralityof flip-flops, formed on an insulating substrate, for generating aplurality of pulse signals whose frequencies are different, insynchronization with a clock signal which is input external to thesubstrate; and a reset circuit, formed on the same substrate as that ofthe plurality of flip-flops, for separately resetting the plurality offlip-flops, which are divided into at least two systems, at differenttimings. An example of this logic circuit includes a timing generationcircuit for generating a plurality of timing signals whose frequenciesare different, in synchronization with a master clock which is inputexternal to the substrate. This timing generation circuit is used as anapplicable timing generation circuit in a display device in which thetiming generation circuit for generating a plurality of timing signalswhose frequencies are different, which are required to drive the displaysection is mounted on the same transparent insulating substrate as thatof the display section. The display device using the timing generationcircuit is incorporated as a screen display section thereof in aportable terminal typified by a PDA (Personal Digital Assistant) and acellular phone.

[0012] In the logic circuit having the above-mentioned configuration,the timing generation circuit using the logic circuit, the displaydevice using the timing generation circuit as one of peripheral drivingcircuits, or the portable terminal having incorporated therein thedisplay device as a screen display section, since a configuration inwhich flip-flops, which are divided into at least two systems, are resetat different timings, is adopted, a resetting operation can be performeddifferently between a flip-flop which needs to be reset at an earliertiming and a flip-flop which needs to be reset at a timing which isdelayed from the above. As a result, since the optimum reset timing canbe set with respect to the respective flip-flops, a large operationmargin can be ensured even when each circuit is formed by usingtransistors having large variations in element characteristics andhaving a rough process rule.

BRIEF DESCRIPTION OF THE DRAWINGS

[0013]FIG. 1 is a circuit diagram showing an example of theconfiguration of a timing generation circuit according to an embodimentof the present invention.

[0014]FIG. 2 is a timing chart illustrating the circuit operation of thetiming generation circuit according to this embodiment.

[0015]FIG. 3 is a timing chart showing in an enlarged manner the mainportion of FIG. 2.

[0016]FIG. 4 is a block diagram showing an example of the configurationof a liquid-crystal display device according to the present invention.

[0017]FIG. 5 is a circuit diagram showing an example of the structure ofa pixel.

[0018]FIG. 6 is an exterior view showing the overview of theconfiguration of a PDA according to the present invention.

[0019]FIG. 7 is a circuit diagram showing an example of theconfiguration of a timing generation circuit according to a conventionalexample.

[0020]FIGS. 8A and 8B are timing charts illustrating the circuitoperation of a timing generation circuit according to a conventionalexample.

BEST MODE FOR CARRYING OUT THE INVENTION

[0021] Embodiments of the present invention will now be described belowin detail with reference to the drawings.

[0022]FIG. 1 is a block diagram showing an example of the configurationof a logic circuit, for example, a timing generation circuit, accordingto an embodiment of the present invention. As is clear from FIG. 1, thetiming generation circuit according to this embodiment includes, forexample, a level-shift circuit 11, two flip-flops (here, TFFs) 12 and13, a level-shift circuit 14, and a pulse generation circuit 15. It ispresupposed that the timing generation circuit is formed on aninsulating substrate such as a glass substrate by using transistors, forexample, TFTs, having large element characteristic variations and havinga rough process rule.

[0023] The level-shift circuit 11 level-shifts (level-converts) a masterclock MCK of a low voltage amplitude (for example, 0 to 3.3 V), which isinput externally, into a master clock lsmck of a high voltage amplitude(for example, 0 to 6.5 V). The master clock lsmck is supplied to the TFF12 and the pulse generation circuit 15, and is supplied via a buffer 16to a circuit which operates by using the master clock lsmck as areference.

[0024] The TFFs 12 and 13 are cascade-connected in sequence to theoutput of the level-shift circuit 11. The TFF 12 generates a dot clockDCK by frequency-dividing the master clock lsmck. This dot clock DCK issupplied via a buffer 17 to a circuit which operates by using the dotclock DCK as a reference. The TFF 13 generates a horizontal clock HCK byfurther frequency-dividing the dot clock DCK. This horizontal clock HCKis supplied to a circuit which operates by using the horizontal clockHCK as a reference.

[0025] Here, in order that the timing of the externally input signal hasa degree of freedom, that is, in order that the input timing is notdetermined as one type, but it is made to have latitude, the resettingoperation of the TFFs 12 and 13 for generating the dot clock DCK and thehorizontal clock HCK must be performed in the period of the externalreference signal (in this example, the period of the horizontalsynchronization signal Hsync), that is, once in one horizontal period.The present invention features a specific configuration of a resetcircuit for resetting the TFFs 12 and 13. The configuration will now bedescribed below.

[0026] The level-shift circuit 14 level-shifts a horizontalsynchronization signal Hsync of a low voltage amplitude (for example, 0to 3.3 V), which is input externally, into a high voltage amplitude (forexample, 0 to 6.5 V), and supplies it to the pulse generation circuit15. The pulse generation circuit 15 detects the edge portion of thehorizontal synchronization signal Hsync after the level-shift, generatesa horizontal synchronization pulse hd in the edge portion in accordancewith the master clock lsmck, and further generates a plurality of resetpulses, that is, two reset pulses drst and hrst corresponding to the twoTFFs 12 and 13 in this example. The reset pulse drst is used to resetthe TFF 12. The reset pulse hrst is used to reset the TFF 13.

[0027]FIG. 2 shows timing relationships among the master clock MCK andthe horizontal synchronization signal Hsync, which are input externally,and the master clock lsmck, the reset pulse drst, the dot clock DCK, thehorizontal synchronization pulse hd, the reset pulse hrst, thehorizontal clock HCK, which are generated within this timing generationcircuit. As is clear from the timing chart of FIG. 2, the reset pulsedrst, the horizontal synchronization pulse hd, and the reset pulse hrst,which are generated within this timing generation circuit 15, aregenerated in accordance with the master clock lsmck by using the falledge as a reference in a period in which the horizontal synchronizationsignal Hsync is at a low level.

[0028] In the timing generation circuit having the above-describedconfiguration, the wiring for the reset pulses drst and hrst has awiring capacity, a transistor input capacity, and a cross capacity withthe other wiring. For this reason, a buffer becomes necessary which hasa driving capability enough to drive such load capacities. As a result,due to the presence of the buffer, a delay occurs in the reset pulsesdrst and hrst. On the other hand, also, in the master clock lsmck, thedot clock DCK, and the horizontal clock HCK, a delay occurs because theypass through the level-shift circuit 11 and the TFFs 12 and 13.

[0029] Here, the number of circuits through which the master clock lsmckpasses is small, and the master clock lsmck has the smallest amount ofdelay. As shown in the flowchart of FIG. 3 (the enlarged view of themain portion of FIG. 2), when it is assumed that, as a result of passingthrough the level-shift circuit 11, an amount of delay Da occurs at themaster clock lsmck with respect to the master clock MCK, if an amount ofdelay Db occurs at the dot clock DCK as a result of passing through theTFF 12, the amount of delay of the dot clock DCK with respect to themaster clock MCK becomes Da+Db. Furthermore, if an amount of delay Dcoccurs at the horizontal clock HCK as a result of passing through theTFF 13, the amount of delay of the horizontal clock HCK with respect tothe master clock MCK becomes Da+Db+Dc.

[0030] In the manner described above, since the amount of delay of themaster clock lsmck is the smallest, it is necessary to reduce the amountof delay as much as possible also with regard to the reset pulse drstfor resetting the TFF 12 which frequency-divides the master clock lsmck.In view of the above, in the timing generation circuit according to thisembodiment, the reset pulse drst is made to be separate from the resetpulse hrst. The arrangement of the pattern of the TFF 12 with respect tothe pulse generation circuit 15 is set to be nearby. As a result, it ispossible to reduce the load capacity of wiring for the reset pulse drst,and a buffer having a smaller driving capability is required as a bufferfor driving the load capacity. Therefore, the amount of delay of thereset pulse drst in the buffer can be reduced.

[0031] Here, as is clear from the timing chart of FIG. 3, the resetpulse drst is generated at the fall timing of the master clock lsmck ina period in which the horizontal synchronization signal Hsync is at alow level. In response to the fall of the master clock lsmck, an amountof delay Dα at the pulse generation circuit 15 occurs in the reset pulsedrst. The reset pulse hrst is generated at a timing relationship whichis delayed further by approximately half a clock of the master clocklsmck from the reset pulse drst.

[0032] While not being limited to the timing relationship between themaster clock lsmck and the reset pulse drst, also with respect to thetiming relationship between the dot clock DCK and the reset pulse hrst,since the reset pulse hrst is a pulse separate from the reset pulsedrst, it is possible to adjust the amounts of delays by adding a bufferif necessary.

[0033] In the timing generation circuit according to this embodiment, asis clear from the timing charts of FIGS. 2 and 3, the TFF 12 generatesthe dot clock DCK as a result of its state being inverted in response tothe fall timing of the master clock lsmck. Similarly, the TFF 13generates the horizontal clock HCK as a result of its state beinginverted in response to the fall timing of the dot clock DCK.

[0034] In the manner described above, in the timing generation circuit,which is formed on an insulating substrate and which has twocascade-connected TFFs 12 and 13, for generating a plurality of timingsignals whose frequencies are different, that is, the dot clock DCK andthe horizontal clock HCK in this example, in synchronization with themaster clock MCK which is input external to the substrate, separatereset pulses drst and hrst are generated with respect to the two TFFs 12and 13. Thus, a resetting operation can be performed differently betweena flip-flop which needs to be reset at an earlier timing and a flip-flopwhich needs to be reset at a timing which is delayed from the above. Asa result, since the optimum reset timing can be set with respect to eachof the TFFs 12 and 13, a large operation margin can be ensured even wheneach circuit is formed by using transistors having large elementcharacteristic variations and having a rough process rule, for example,TFTs.

[0035] Here, as is clear from the timing charts of FIGS. 2 and 3, whenthe delay of the timing of the reset pulse drst becomes larger, and thereset pulse drst rises in a period in which the master clock lsmck is ata low level, the dot clock DCK shifts from a low level to a high levelat the fall timing of the next master clock lsmck, and therefore, thepolarity of the dot clock DCK after the resetting operation inaccordance with the reset pulse drst is inverted.

[0036] In the above-described embodiment, the logic circuit has beendescribed by using the timing generation circuit as an example. Thepresent invention is not limited to the application to the timinggeneration circuit, and can be applied to logic circuits in general forgenerating a plurality of pulse signals whose frequencies are differentin synchronization with a single clock signal by using a plurality offlip-flops which are cascade-connected.

[0037] A circuit configuration in which flip-flops are cascade-connectedat two stages has been used as an example; applications are similarlypossible to a circuit configuration in which flip-flops arecascade-connected at three or more stages so as to generate three ormore pulse signals whose frequencies are different. Also, in this case,flip-flops at three or more stages may be divided into at least twosystems, and may be reset separately at mutually different timings.

[0038] Furthermore, in a case where a clock having large variations inthe amount of delay is put in the flip-flop, when the reset pulse ismade to be a pulse having a relatively small variation in the amount ofdelay with respect to the input clock, the operation speed can beincreased.

[0039] The timing generation circuit according to the above-describedembodiment is suitably used as, for example, a timing generator forgenerating various timing signals which are required to drive thedisplay section in accordance with the master clock MCK which is inputexternal to the substrate, in a driving-circuit-integrated displaydevice such that peripheral driving circuits are integrally formed onthe same transparent insulating substrate as that of the display sectionhaving pixels arranged thereon in a matrix.

APPLICATION EXAMPLE

[0040]FIG. 4 is a block diagram showing an example of the configurationof a display device, for example, a liquid-crystal display device,according to the present invention. In FIG. 4, on a transparentinsulating substrate, for example, a glass substrate 31, a displaysection (pixel section) 32 having pixels arranged thereon in a matrix isformed. The glass substrate 31 is opposedly arranged with apredetermined spacing with another glass substrate, and a display panel(LCD panel) is formed by sealing a liquid-crystal material between thetwo substrates.

[0041] An example of the structure of each pixel at the display section32 is shown in FIG. 5. Each pixel 50 arranged in a matrix is configuredto have a TFT (Thin-Film Transistor) 51, which is a pixel transistor; aliquid-crystal cell 52 whose pixel electrode is connected to the drainelectrode of the TFT 51; and a holding capacitor 53, one of electrodesof which is connected to the drain electrode of the TFT 51. Here, theliquid-crystal cell 52 means a liquid-crystal capacitance generatedbetween the pixel electrode and the opposing electrode formed so as tooppose the pixel electrode.

[0042] In this pixel structure, the gate electrode of the TFT 51 isconnected to a gate line (scanning line) 54, and the source electrodethereof is connected to a data line (scanning line) 55. The opposingelectrode of the liquid-crystal cell 52 is connected to a VCOM line 56in such a manner as to be common for each pixel. Then, a common voltageVCOM (VCOM potential) is supplied to the opposing electrode of theliquid-crystal cell 52 commonly for each pixel via the VCOM line 56. Theother electrode (the terminal on the opposing electrode side) of theholding capacitor 53 is connected to a CS line 57 in such a manner as tobe common for each pixel.

[0043] Here, in a case where 1H (H is a horizontal period) inverteddriving or 1F (F is a field period) inverted driving is to be performed,the polarity of a display signal to be written into each pixel isinverted with the VCOM potential being used as a reference. Furthermore,in a case where VCOM inverted driving in which the polarity of the VCOMpotential is inverted in a 1H period or a 1F period is used togetherwith 1H inverted driving or 1F inverted driving, the polarity of the CSpotential given to the CS line 57 is also inverted in synchronizationwith the VCOM potential. However, the liquid-crystal display deviceaccording to this embodiment is not limited to VCOM inverted driving.

[0044] Referring back to FIG. 4, on the same glass substrate 31 as thatof the display section 32, for example, an interface (IF) circuit 33, atiming generator (TG) 34, and a reference voltage driver 35 areincorporated to the left of the display section 32; a horizontal driver36 is incorporated in the upper portion of the display section 32; avertical driver 37 is incorporated to the right of the display section32; and a CS driver 38 and a VCOM driver 39 are incorporated in thelower portion of the display section 32. These peripheral drivingcircuits are manufactured by using low-temperature polysilicon or CG(continuous-grain-boundary crystal) silicon together with the pixeltransistors of the display section 32.

[0045] In the liquid-crystal display device having the above-describedconfiguration, a master clock MCK of a low voltage amplitude (forexample, 3.3 V), a horizontal synchronization pulse Hsync, a verticalsynchronization pulse Vsync, and display data Data of parallel input ofR (red), G (green), and B (blue) are input via a flexible cable(substrate) 40 to the glass substrate 31 from outside the substrate, andthe display data Data is level-shifted (level-converted) to a highvoltage amplitude (for example, 6.5 V) at the IF circuit 33.

[0046] The level-shifted master clock MCK, horizontal synchronizationpulse Hsync, and vertical synchronization pulse Vsync are supplied tothe timing generator 34. Based on the master clock MCK, the horizontalsynchronization pulse Hsync, and the vertical synchronization pulseVsync, the timing generator 34 generates various timing pulses requiredto drive the reference voltage driver 35, the horizontal driver 36, thevertical driver 37, the CS driver 38, and the VCOM driver 39.

[0047] The level-shifted display data Data is supplied to aserial-to-parallel (S/P) conversion circuit 42 at the next stage. Theserial-to-parallel conversion circuit 42 lowers the frequency of thedisplay data Data to ½ by converting the display data Data into two bitsfor each bit in synchronization with a dot clock DCK (to be describedlater) supplied from the timing generator 34. The display data whosefrequency is lowered at the serial-to-parallel conversion circuit 42 islowered to a low voltage amplitude of 0 to 3.3 V, and is supplied to thehorizontal driver 36.

[0048] The horizontal driver 36 is configured to have, for example, ahorizontal shift register 361, a data sampling latch circuit 362, and aDA (digital-to-analog) conversion circuit (DAC) 363. The horizontalshift register 361 starts a shift operation in response to a horizontalstart pulse HST supplied from the timing generator 34, and generates asampling pulse which is transferred in sequence during one horizontalperiod in synchronization with a horizontal clock HCK which is similarlysupplied from the timing generator 34.

[0049] The data sampling latch circuit 362 sequentially samples andlatches the display data Data supplied from the interface circuit 33 viaa serial-to-parallel conversion circuit 43 during one horizontal periodin synchronization with the sampling pulse generated at the horizontalshift register 361. This latched digital data for one line is furthertransferred to a line memory (not shown) during a horizontal blankingperiod. Then, the digital data for one line is converted into an analogdisplay signal at the DA conversion circuit 363.

[0050] The DA conversion circuit 363 is configured as areference-voltage-selection-type DA conversion circuit for selecting areference voltage corresponding to digital data from among the referencevoltages for the number of gradations provided from the referencevoltage driver 35 and for outputting the reference voltage as an analogdisplay signal. The analog display signals Sig for one line, which areoutput from the DA conversion circuit 363, are output to data lines 55-1to 55-n which are wired in such a manner as to correspond to the numberof horizontal pixels n of the display section 32.

[0051] The vertical driver 37 is formed of a vertical shift register anda gate buffer. At this vertical driver 37, the vertical shift registerstarts a shift operation in response to a vertical start pulse VSTsupplied from the timing generator 34, and generates a scanning pulsewhich is transferred in sequence during one vertical period insynchronization with a vertical clock pulse VCK, which is similarlysupplied from the timing generator 34. The generated scanning pulses areoutput in sequence through the gate buffer to gate lines 54-1 to 54-mwhich are wired in such a manner as to correspond to the number ofvertical pixels m of the display section 32.

[0052] When the scanning pulses are output in sequence to the gate lines54-1 to 54-m as a result of vertical scanning by the vertical driver 37,each pixel of the display section 32 is selected in sequence in units ofrows (lines). Then, the analog display signals Sig for one line, whichare output from the DA conversion circuit 363, are simultaneouslywritten into the selected pixels for one line via the data lines 55-1 to55-n. As a result of this writing operation in units of lines beingrepeated, an image display for one screen is made.

[0053] The CS driver 38 generates the above-mentioned CS potential, andprovides it commonly to the pixels with respect to the other electrodeof the holding capacitor 53 via the CS line 57 of FIG. 5. Here, if theamplitude of the display signal is assumed to be, for example, 0 to 3.3V, when VCOM inverted driving is adopted, the CS potential repeats ACinversion between a low level of 0 V (ground level) and a high level of3.3 V.

[0054] The VCOM driver 39 generates the above-mentioned VCOM potential.The VCOM potential output from the VCOM driver 39 is temporarily outputoutside the glass substrate 31 via a flexible cable 40. After this VCOMpotential which is output outside the substrate is passed through a VCOMadjustment circuit 41, it is input again into the glass substrate 31 viathe flexible cable 40, and is supplied commonly to the pixels withrespect to the opposing electrode of the liquid-crystal cell 52 via theVCOM line 56 of FIG. 5.

[0055] Here, as the VCOM potential, an AC voltage having nearly the sameamplitude as that of the CS potential is used. However, in practice, inFIG. 5, when a signal is written into the pixel electrode of theliquid-crystal cell 52 through the TFT 51 from the data line 54, avoltage drop occurs at the TFT 51 due to parasitic capacitance, etc. Forthis reason, as the VCOM potential, an AC voltage which is DC-shifted byan amount corresponding to that voltage drop needs to be used. This DCshift of the VCOM potential is burdened by the VCOM adjustment circuit41.

[0056] The VCOM adjustment circuit 41 is formed of a capacitor C whichinputs VCOM potential; a variable resistor VR which is connected betweenthe output end of the capacitor C and an external power-supply VCC; anda resistor R which is connected between the output end of the capacitorC and a ground. The VCOM adjustment circuit 41 adjusts the DC level ofthe VCOM potential supplied to the opposing electrode of theliquid-crystal cell 52, that is, applies an DC offset to the VCOMpotential.

[0057] In the liquid-crystal display device having the above-describedconfiguration, on the same panel (the glass substrate 31) as that of thedisplay section 32, in addition to the horizontal driver 36 and thevertical driver 37, peripheral driving circuits, such as the interfacecircuit 33, the timing generator 34, the reference voltage driver 35,the CS driver 38, and the VCOM driver 39, are integrally mounted,thereby forming a total-driving-circuit-integrated display panel. Thus,since other substrates, ICs, transistor circuits need not to be providedoutside, the entire system can be reduced in size, and the cost thereofcan be reduced.

[0058] In this driving-circuit-integrated liquid-crystal display device,as a timing generator 34 for generating various timing signals fordriving the display section 32, the timing generation circuit accordingto the above-described embodiment is used. In the timing generationcircuit shown in FIG. 1, the level-shift circuits 11 and 14 correspondto the interface circuit 33, and the TFFs 12 and 13, the pulsegeneration circuit 15, and the buffers 16 and 17 correspond to thetiming generator 34.

[0059] Then, the master clock lsmck which is level-shifted at thelevel-shift circuit 11 is supplied to a circuit which operates by usingthe master clock lsmck as a reference, more specifically, the datasampling latch circuit 362 of the horizontal driver 36. Furthermore, thedot clock DCK generated at the TFF 12 is supplied to a circuit whichoperates by using the dot clock DCK as a reference, more specifically,the serial-to-parallel conversion circuit 42. The horizontal clock HCKgenerated at the TFF 13 is supplied to a circuit which operates by usingthe horizontal clock HCK as a reference, more specifically, thehorizontal shift register 361 of the horizontal driver 36.

[0060] In the manner described above, by using the timing generationcircuit according to the above-described embodiment as the timinggenerator 34, in the timing generation circuit, even when each circuitis formed on an insulating substrate by using transistors having largeelement characteristic variations and having a rough process rule, alarge operation margin can be ensured. As a result, it is possible tomanufacture a liquid-crystal display device having a large operationmargin, which is formed in such a manner that peripheral drivingcircuits are formed on a transparent insulating substrate integrallywith the glass substrate 31 by using TFTs.

[0061] In this application example, a case of applications to aliquid-crystal display device including liquid-crystal cells asliquid-crystal elements has been described as an example. While notbeing limited to this application example, applications are possible todisplay devices in general having mounted a level-shift circuit on thesame substrate as that of the display section, such as an EL displaydevice including EL (Electroluminescent) elements as display elements.

[0062] The display device typified by the liquid-crystal display deviceaccording to the above-described application example is suitably used asa screen display section of a small and lightweight portable terminaltypified by a cellular phone and a PDA (Personal Digital Assistant).

[0063]FIG. 6 is an exterior view showing the overview of theconfiguration of a portable terminal, for example, a PDA, according tothe present invention.

[0064] The PDA according to this example has a folding configuration inwhich, for example, a lid 62 is provided so as to be openable andclosable with respect to the main unit 61 of the device. On the topsurface of the main unit 61 of the device, an operation section 63 onwhich various keys of a keyboard are arranged is placed. On the otherhand, in the lid 62, a screen display section 64 is arranged. As thisscreen display section 64, a liquid-crystal display device in which thetiming generation circuit according to the above-described embodiment ismounted as a timing generator on the same substrate as that of thedisplay section is used.

[0065] By using the timing generation circuit according to theabove-described embodiment as a timing generator of the liquid-crystaldisplay device, a driving-circuit-integrated liquid-crystal displaydevice having a large operation margin can be formed. As a result, byincorporating the liquid-crystal display device as the screen displaysection 64, the configuration of the entire PDA can be simplified,making it possible to contribute to a reduction in size and a reductionin cost.

[0066] Here, although a description has been given by using a case inwhich the present invention is applied to a PDA as an example, thepresent invention is not limited to this application example. Theliquid-crystal display device according to the present invention issuitably used for, in particular, small and lightweight portableterminals in general, such as cellular phones.

INDUSTRIAL APPLICABILITY

[0067] As has thus been described, according to the present invention,in the timing generation circuit, which is formed on an insulatingsubstrate and which has a plurality of flip-flops, for generating aplurality of timing signals whose frequencies are different insynchronization with a clock signal which is input external to thesubstrate, the plurality of flip-flops are divided into at least twosystems and are reset separately at different timings. Thus, a resettingoperation can be performed differently between a flip-flop which needsto be reset at an earlier timing and a flip-flop which needs to be resetat a timing which is delayed from the above. As a result, since theoptimum reset timing can be set with respect to the respectiveflip-flops, a large operation margin can be ensured even when eachcircuit is formed by using transistors having large elementcharacteristic variations and having a rough process rule.

1. A logic circuit comprising: a plurality of flip-flops, formed on aninsulating substrate, for generating a plurality of pulse signals whosefrequencies are different, in synchronization with a clock signal whichis input external to the substrate; and a reset circuit, formed on thesame substrate as that of said plurality of flip-flops, for separatelyresetting said plurality of flip-flops, which are divided into at leasttwo systems, at different timings.
 2. A timing generation circuitcomprising: a plurality of flip-flops, formed on an insulatingsubstrate, for generating a plurality of pulse signals whose frequenciesare different, in synchronization with a master clock which is inputexternal to the substrate; and a reset circuit, formed on the samesubstrate as that of said plurality of flip-flops, for separatelyresetting said plurality of flip-flops, which are divided into at leasttwo systems, at different timings.
 3. A display device comprising: adisplay section having pixels arranged in a matrix on a transparentinsulating substrate; and a timing generation circuit, mounted on saidtransparent insulating substrate together with said display section, forgenerating a plurality of timing signals whose frequencies aredifferent, which are required to drive said display section, insynchronization with a master clock which is input external to thesubstrate, wherein said timing generation circuit comprises: a pluralityof flip-flops for generating said plurality of timing signals in acorresponding manner; and a reset circuit for separately resetting saidplurality of flip-flops, which are divided into at least two systems, atdifferent timings.
 4. A display device according to claim 3, whereinsaid timing generation circuit is formed on said transparent insulatingsubstrate by using low-temperature polysilicon orcontinuous-grain-boundary crystal silicon.
 5. A portable terminal havingincorporated therein a display device as a screen display section, saiddisplay device comprising: a display section having pixels arranged in amatrix on a transparent insulating substrate; and a timing generationcircuit, mounted on said transparent insulating substrate together withsaid display section, for generating a plurality of timing signals whosefrequencies are different, which are required to drive said displaysection, in synchronization with a master clock which is input externalto the substrate, wherein said timing generation circuit comprises: aplurality of flip-flops for generating said plurality of timing signalsin a corresponding manner; and a reset circuit for separately resettingsaid plurality of flip-flops, which are divided into at least twosystems, at different timings.